PCIe broke this paradigm by adopting a . Instead of a wide, shared bus, PCIe uses point-to-point connections called lanes . A single lane consists of two differential signal pairs: one for transmitting and one for receiving, allowing full-duplex communication. By moving to a serial design, PCIe eliminated bus contention and clock skew, enabling data rates to scale dramatically with improvements in physical layer technology.
: A core tenet of the specification is that newer versions remain compatible with older hardware and software. For instance, a PCIe 3.0 GPU will function in a PCIe 4.0 or 5.0 slot , albeit at the lower generation's speed. Evolution of PCIe Generations pci express specification
This is the lowest layer, responsible for the actual transmission of bits. PCIe broke this paradigm by adopting a
The PCIe specification is backward compatible, meaning a PCIe 4.0 device will work in a PCIe 3.0 slot (though at 3.0 speeds). Below is the evolution of raw bandwidth per lane: By moving to a serial design, PCIe eliminated