The worst mistake in digital design is generating a “derived clock” using combinational logic or a register output as a clock for other flip-flops. This creates:
always @(posedge clk) begin if (clk_en) begin // do something every 8 clocks end end
reg [31:0] counter; // counter to keep track of clock cycles
💡 If your FPGA has Phase-Locked Loops (PLLs) or Mixed-Mode Clock Managers (MMCMs), use them for frequency division whenever possible. Hardware-based dividers provide: Low jitter. Precise phase alignment. The ability to multiply as well as divide.
