The clock lane can also independently enter ULPS, putting the clock lane into the LP-00 state, effectively halting the high-speed clock to the receiver. ULPS Exit Sequence
Implementing ULPS requires sophisticated power management logic in the display driver software (kernel drivers). The operating system must intelligently decide when to enter ULPS (e.g., after the frame buffer has been flushed and no updates are pending) and when to preemptively wake the display before the next frame is ready. mipi ulps